(When) Will CMPs Hit the Power Wall?

Currently the power wall is one of the major obstacles chip industry is facing. At the same time processor architecture shifts towards chip multiprocessors (CMPs), which are believed to alleviate the power problem. In this paper we analyze the impact of the power wall on CMP design. As a case study we model a CMP consisting of Alpha 21264 cores, scaled to future technology nodes according to the ITRS roadmap. In 2020 such a CMP would contain 625 cores, and when running on the maximum possible frequency of 73 GHz would consume 7 kW , while the power budget is predicted to be 198 W . From these figures it is clear that power will be a major bottleneck for performance increase. However, we also calculated the power constrained performance increase which shows that technology improvements enables a doubling of performance increase every three years for CMPs. Overhead and limited amounts of available thread level parallelism eventually cause this increase to flatten out. At the architectural level, performance can be increased by designing for power efficiency. We conclude from this study that for the next decade CMPs can provide significant performance increases without hitting the power wall.